EMG Signal Acquisition & Processing
A complete EMG pipeline—sensor capture, microcontroller streaming, and Python processing/visualization for clean, usable muscle-signal data.
From Raw EMG to Clean Features
I built a reliable acquisition + analysis workflow for EMG signals: capturing raw sensor output, streaming it through a microcontroller, and processing it in Python for visualization and feature extraction.
A complete EMG workflow: sensor capture → microcontroller streaming → Python processing, with live plotting, noise reduction, and basic metrics for consistent tracking across trials.
EMG is noisy and inconsistent. The main challenges were stabilizing capture, reducing motion/line noise, and producing outputs that reflect real activation rather than artifacts.
How to design “lab reliable” tooling: consistent sampling, clean data paths, repeatable processing, and visuals that support decisions.
Key Features
- Reliable EMG data streaming
- Live plotting + monitoring
- Filtering / noise reduction
- Feature extraction basics
- Repeatable workflow
- Portfolio-ready tooling
Autonomous / IoT Robotic Car
An embedded robotics platform with motor control, sensors, and wireless control—built to be modular, testable, and easy to extend.
Motor Control, Sensing, and Wireless Control
I designed a robotic-car platform around a microcontroller, focusing on reliable motor control, modular sensor integration, and a wireless control path for remote operation and testing.
A robotic car with a structured embedded codebase: motor control, sensor reads, and a wireless input layer designed to be easy to extend.
Smooth predictable motion + stable sensing + wireless control. Focus areas: power stability, noise, and consistent behavior.
Integration is the real work: grounding, wiring discipline, sensor noise, and code structure matter as much as features.
Key Features
- Motor driver control
- Sensor integration
- Modular code structure
- Wireless control layer
- Repeatable testing
- Clean hardware integration
Synchronous FIFO (RTL + Verification)
A clean, parameterized FIFO design with self-checking verification—focused on correctness, edge cases, and hardware-real behavior.
Correct FIFO Behavior Under Real Conditions
I implemented a synchronous FIFO with correct full/empty behavior, clean pointer logic, and a self-checking testbench. The focus was correctness under edge cases: simultaneous read/write, boundary transitions, and illegal operation prevention.
A parameterized FIFO module (width and depth) using read/write pointers and occupancy tracking, with explicit full and empty flags. The design cleanly separates pointer updates, flag logic, and data storage to match real hardware behavior.
The FIFO supports configurable DATA_WIDTH and DEPTH, safely handles simultaneous read and write operations in the same cycle, and is verified using a self-checking testbench with a software reference model and scoreboard to validate correctness under randomized traffic.
The hardest part is defining “correct” behavior when signals overlap: read + write in the same cycle, full-to-not-full transitions, and preventing reads on empty / writes on full. The design was written to match how real flip-flops update state on a clock edge.
Good verification forces clarity. Writing a reference model + automated checks made bugs obvious fast, and it taught me to think in terms of cycle-accurate behavior and corner cases—not just “works in one demo”.
Key Features
- Parameterized width/depth
- Correct full/empty flags
- Safe simultaneous R/W
- Self-checking testbench
- Scoreboard + reference model
- Waveform-driven debugging
FPGA Arithmetic Display System
A digital system combining a datapath and control logic to perform arithmetic operations and display results on a 7-segment interface.
Datapath + Controller That Scales
This project focuses on clean digital architecture: a datapath that performs arithmetic and a controller (FSM) that sequences inputs and operations, with stable output shown through 7-segment display logic.
I designed a structured FPGA-based arithmetic system composed of a datapath and a controller, following clean digital design principles. The datapath handles operand storage, arithmetic operations, and result formatting, while a finite-state machine (FSM) sequences input capture, computation, and display updates.
The system drives a 7-segment display using dedicated encoding logic, ensuring stable and readable outputs. Emphasis was placed on separating combinational and sequential logic, maintaining glitch-free display behavior, and keeping module boundaries clean to support debugging, reuse, and future feature expansion.
Keeping the system “hardware-clean”: separating combinational vs sequential logic, ensuring stable outputs, and making sure the display updates at the right time without glitching or meta-behavior from noisy inputs.
Modular RTL makes everything easier: debugging, reuse, and scaling features. Once the datapath/control split is correct, future additions (new ops, input handling, display modes) are straightforward.
Key Features
- Datapath/control split
- FSM sequencing
- Stable output timing
- 7-segment encoding
- Clean modular RTL
- Simulation + debug workflow
Mini-Lysimeter Research GUI
A research-oriented Python GUI integrating DAQ hardware and microcontroller inputs to collect, monitor, and export experimental data.
A Research-Friendly Data Capture Tool
I built a Python GUI to support experiments by connecting to DAQ hardware and microcontroller inputs. The focus is usability and reliability: live monitoring, simple controls, and clean exports for analysis.
I developed a Python-based graphical user interface to support laboratory experiments by integrating NI-DAQ hardware and microcontroller inputs. The tool allows users to configure acquisition channels, monitor sensor signals in real time, and maintain visibility into experiment health during data collection.
The interface emphasizes reliability and usability: predictable acquisition behavior, clear status feedback, and clean CSV data exports for downstream analysis. Design decisions focused on reducing manual steps, handling connection failures gracefully, and providing a workflow that researchers can trust during live experiments.
Making the tool stable under real lab usage: connection failures, sampling consistency, and a UI that stays responsive. This meant focusing on error handling, clear status, and predictable acquisition behavior.
The best tools are boring-in-a-good-way: clear workflows, meaningful error states, and exports that match what analysis needs. “Reliable and repeatable” beats “flashy” for research software.
Key Features
- Live monitoring
- Device configuration
- Clean CSV exports
- Research-friendly UI
- Stable acquisition flow
- Practical error handling
Simon-Says Memory Game (Arduino)
A handheld multi-mode Simon-style memory game with sound control, debounced inputs, and EEPROM high score saving—built fast, refined for usability, and packaged in a custom physical enclosure.
A Handheld Simon Game Built to Feel “Real”
I developed a Simon-Says memory game on Arduino in under two days, then iterated on both the software and physical design to make it more playable, reliable, and portable. The final version supports multiple game modes, sound control, and persistent high score tracking.
I built a complete Simon game system with a clear gameplay loop: generate sequences, present them using LEDs and tones, accept user input, validate correctness, and track progression using a level/score system. The firmware includes multiple play styles (Classic, Speed, Reverse, and Stealth), a lives system, and a mute toggle for sound control.
To make the device feel polished rather than prototype-only, I added debounced button handling, an I2C LCD interface for readable prompts and feedback, and EEPROM-based high score saving so the best score persists across power cycles. I also designed the physical enclosure in Autodesk Inventor and used hands-on fabrication/woodworking to build the game box and later refine it into a handheld “Gameboy-style” form factor.
The biggest challenge was making the game reliable and responsive under real use. Without debouncing, button presses can double-trigger, and timing-sensitive modes can become frustrating rather than fun. I also had to keep the UI readable and avoid confusing state transitions while still supporting multiple modes and gameplay rules.
On the hardware side, I iterated on the enclosure to balance usability and portability. The first design focused on a full game-box experience, then I simplified the physical layout into a handheld version while keeping the interaction clear: consistent button placement, obvious LED feedback, and sound cues that match the game state.
This project taught me how fast prototyping and clean system thinking can work together. Building the first playable version quickly was useful, but the real improvement came from iteration: tightening state logic, adding robust input handling, and making the UI clearer so the device is enjoyable and predictable.
I also learned how much physical design affects software perception. Even simple electronics feel “finished” when the enclosure, input layout, and feedback are intentional. The result is a small embedded product that demonstrates both firmware structure and real-world hardware integration.
Key Features
- Classic, Speed, Reverse, Stealth modes
- Lives + scoring progression
- Debounced input handling
- EEPROM high score persistence
- LCD prompts + feedback
- Custom Inventor enclosure design